1. Field of the Invention
The present invention relates to a delay time control circuit. Particularly, the present invention relates to a delay time control circuit capable of setting an amount of delay with high precision in a linear correspondence at both a leading edge and trailing edge of a pulse signal such as data and/or clock signal and, particularly, capable of setting an appropriate delay time for a write data in a CD-R/RW (CD-Recordable/Re-Writable) device.
2. Description of the Related Art
A data write speed of a recent CD-R/RW device has been increased remarkably.
The CD-R/RW device receives write data transferred from a host computer through an interface such as an SCSI (Small Computer System Interface) or an ATPI, EFM-modulates it and adds a modulated write data to a laser controller internally thereof. A laser light is on-off controlled for a write operation by the laser controller correspondingly to the EFM-controlled data and irradiates a predetermined track of a CD to form pits in the track to thereby write the data in the CD. The thus written data is read out by irradiating the track with a laser light controlled for read and receiving a light reflected from the pits by a light receiving element. The CD-R/RW device obtains the original data as a read-out data by demodulating the EFM-modulated signal received by the light receiving element and amplified by a read-out amplifier and transfers the read-out data to the host computer through the SCSI or ATPI.
In this case, in writing the EFM-modulated data in the CD, a length of a write time of the write data and a period of the data or the clock depends upon the write speed. Therefore, a timing regulation of the data or the clock becomes necessary. The timing regulation is performed by a delay circuit. In the case of the write operation of such as a CD-R/RW device, the timing regulation has to be performed with high precision. Furthermore, the timing regulation has to be performed by controlling the amount of delay at both a leading edge and a trailing edge of a pulse signal (1 bit) of such as the data or the clock signal with a preciseness corresponding to the write speed.
As shown in FIG. 2, a conventional delay time control circuit 10 for this purpose is constructed with a plurality of series-connected delay circuits Da to Dh, a selector 11 and a decoder 12. The delay circuits Da to Dh provide an appropriate amount of delay corresponding to the number of the delay circuits starting from the first delay circuit Da having an input used an input terminal IN of the delay time control circuit 10. The selector 11 receives outputs of the delay circuits Da to Dh, selects one of the outputs corresponding to a selection control signal SEL and outputs a signal having an aimed amount of delay with respect to the input signal at an output terminal OUT of the delay time control circuit 10. The selection control signal SEL is produced by decoding data sent from a controller, etc., by using the decoder 12. The selector 11 is constructed with AND gates and OR gates.
In the delay time control circuit 10 constructed with such AND gates and the OR gates, the gate operation when the signal input to the input terminal IN is HIGH level differs from that when the input signal is LOW level. Further, due to a difference between gate circuits, which operate in response to a selected output, it is impossible to select a total delay time in a linear relation. Therefore, a delay time in a leading edge of a pulse signal of one bit such as data or clock, etc., becomes different from that in a trailing edge thereof, causing a data error tend to occur.